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| 1. general description the px1041a is a high-performance, low-power, four-lane pci express electrical physical layer (phy) that handles the low level pci express protocol and signaling. the px1041a pci express phy is compliant to the pci express base speci?cation, rev. 1.0a , and rev. 1.1 . the px1041a includes features such as clock and data recovery (cdr), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the media access control (mac) layer devices. the px1041a is a 2.5 gbit/s pci express phy with 4 8-bit data pxpipe interface. its pxpipe interface is a superset of the phy interface for the pci express (pipe) speci?cation, enhanced and adapted for off-chip applications with the introduction of a source synchronous clock for transmit and receive data. the 4 8-bit data interface operates at 250 mhz with sstl class i signaling at 2.5 v or 1.8 v. the sstl signaling is compatible with the i/o interfaces available in fpga products. the px1041a pci express phy supports advanced power management functions. the px1041ai is for the industrial temperature range ( - 40 c to +85 c). 2. features 2.1 pci express interface n compliant to pci express base speci?cation 1.0a and 1.1 n four pci express 2.5 gbit/s lane n data and clock recovery from serial stream n serializer and de-serializer (serdes) n receiver detection n 8b/10b coding and decoding, elastic buffer and word alignment n supports direct disparity control for use in transmitting compliance pattern n supports lane polarity inversion n low jitter and bit error rate (ber) n supports pci express-side parallel loopback n supports pxpipe-side parallel loopback n supports receiver lane-to-lane deskew (optional) n supports lane reversal (optional) 2.2 phy/mac interface n based on intel phy interface for pci express architecture v2.0 (pipe) n adapted for off-chip with additional synchronous clock signals (pxpipe) px1041a pci express stand-alone x4 phy rev. 01 21 june 2007 objective data sheet
px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 2 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy n pipe mode selectable n 4 8-bit parallel data interface for transmit and receive at 250 mhz n sstl class i signaling at 2.5 v or 1.8 v, without select pin 2.3 jtag interface n jtag (ieee 1149.1) boundary scan interface n built-in self test (bist) controller tests serdes and i/o blocks at speed n 3.3 v cmos signaling 2.4 power management n dissipates < 1 w in l0 normal mode n support power management of l0, l0s, l1, and l2 2.5 clock n 100 mhz external reference clock with 300 ppm tolerance n supports spread spectrum clock to reduce emi n on-chip reference clock termination 2.6 miscellaneous n lfbga208 lead free package n operating ambient temperature u px1041a for commercial range: 0 c to +70 c u px1041ai for industrial range: - 40 c to +85 c n esd protection voltage for human body model (hbm): 2000 v 3. quick reference data [1] no select pin needed. table 1. quick reference data symbol parameter conditions min typ max unit v ddd1 digital supply voltage 1 for jtag i/o 3.0 3.3 3.6 v v ddd2 digital supply voltage 2 for sstl_18 i/o [1] 1.7 1.8 1.9 v for sstl_2 i/o [1] 2.3 2.5 2.7 v v ddd3 digital supply voltage 3 for core 1.15 1.2 1.25 v v dd supply voltage for high-speed serial i/o and pvt 1.15 1.2 1.25 v v dda1 analog supply voltage 1 for serializer 1.15 1.2 1.25 v v dda2 analog supply voltage 2 for serializer 3.0 3.3 3.6 v f clk(ref) reference clock frequency 99.97 100 100.03 mhz t amb ambient temperature operating commercial 0 - +70 c industrial - 40 - +85 c px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 3 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 4. ordering information 5. marking [1] industrial temperature range. table 2. ordering information type number solder process package name description version PX1041A-EL1/g pb-free (snagcu solder ball compound) lfbga208 plastic low pro?le ?ne-pitch ball grid array package; 208 balls; body 15 15 1mm sot631-4 px1041ai-el1/g pb-free (snagcu solder ball compound) lfbga208 plastic low pro?le ?ne-pitch ball grid array package; 208 balls; body 15 15 1mm sot631-4 table 3. lead-free package marking line marking description a PX1041A-EL1/g px1041ai-el1/g [1] full basic type number b xxxxxxx diffusion lot number c 2pgyyww manufacturing code: 2 = diffusion site p = assembly site g = lead-free yy = year code ww = week code px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 4 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 6. block diagram fig 1. block diagram of px1041a 8 10 002aac432 ln_txdata0 tx i/o refclk i/o refclk_p register pci express phy pci express mac ln_txdata1 reset_n l0_rxdata [ 7:0 ] l0_txdata [ 7:0 ] txclk 8b/10b encode 10b/8b decode refclk_n l0_tx_p l0_tx_n rx i/o l0_rx_p bit stream at 2.5 gbit/s l0_rx_n elastic buffer k28.5 detection clock recovery circuit pll clk generator 250 mhz clock parallel to serial serial to parallel data recovery circuit lane 0 lane 1 l1_txdata[7:0] l1_rxdata[7:0] l1_tx_p rxclk l1_tx_n l1_rx_p l1_rx_n lane 2 l2_txdata[7:0] l2_rxdata[7:0] l2_tx_p l2_tx_n l2_rx_p l2_rx_n lane 3 l3_txdata[7:0] l3_rxdata[7:0] l3_tx_p l3_tx_n l3_rx_p l3_rx_n px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 5 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 7. pinning information 7.1 pinning fig 2. pin con?guration for lfbga208 002aac433 PX1041A-EL1/g px1041ai-el1/g transparent top view ball a1 index area u t r p n m k h l j g f e d c a b 24681012 13 14 15 17 16 1357911 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 6 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy transparent top view. fig 3. ball mapping 1 a refclk_p tms tdi l0_ rxdata7 l0_ rxdata5 l0_ rxdata4 l0_ rxdata2 l0_ rxdata0 l0_ txdata7 23456789 b refclk_n trst_n tck v ss l0_ rxdata6 l0_ rxdata3 v ss l0_ rxdata1 l0_ txdata6 c v ss v ddd1 tdo l0_ rxdatak l0_ rxvalid l0_ rxpol l0_ txcomp d l0_rx_p v ss pvt l0_ rxidle l0_ rxstatus2 v ss v ddd2 v ddd2 e l0_rx_n v ss v ss v dda2 f v ss v ss l0_tx_p v dd g l1_rx_p v ss l0_tx_n v dd h l1_rx_n v ss v ss v dd j v ss v ss l1_tx_p v dda1 k l2_rx_p v ss l1_tx_n v dda1 l l2_rx_n v ss v ss v dda1 m v ss v ss l2_tx_p v dda1 n l3_rx_p v ss l2_tx_n v dda1 p l3_rx_n v ss v ss l3_ txcomp l3_ rxpol v ss v ddd3 v ddd3 v ss r v ss v ss l3_ txdata0 l3_ txidle l3_ txdatak l3_ rxvalid l3_ rxstatus2 t l3_tx_p v ss l3_ txdata1 v ss l3_ txdata4 l3_ txdata6 v ss l3_ rxdata2 l3_ rxdata3 u l3_tx_n v ss l3_ txdata2 l3_ txdata3 l3_ txdata5 l3_ txdata7 l3_ rxdata0 l3_ rxdata1 l3_ rxdata4 002aac434 l0_ txdata5 l0_ txdata4 l0_ txdata2 reset_n rxclk txclk l1_ rxdata7 l1_ rxdata6 10 11 12 13 14 15 16 17 v ss l0_ txdata3 l0_ txdata1 v ss pwrdwn1 deskew_ start v ss l1_ rxdata5 l0_ txdatak l0_ txidle l0_ txdata0 pipeloopb pwrdwn0 l1_ rxdatak l1_ rxdata4 v ddd2 v ddd2 encoding en pipemode sel v ss phystatus l1_ rxidle l1_ rxdata3 lane reversal rxdet_ loopb v ss l1_ rxdata2 l1_ rxvalid l1_ rxdata1 l1_ rxdata0 v ddd2 v ss l1_ txdata7 v ddd2 l1_ rxstatus0 l1_ txdata5 l1_ txdata6 v ddd2 l1_ rxpol l1_ txdata3 l1_ txdata4 v ddd2 l1_ txdatak v ss l1_ txdata2 l1_ txcomp l1_ txidle l1_ txdata1 l1_ txdata0 l2_ rxvalid l2_ rxidle l2_ rxdatak l2_ rxdata7 l2_ rxpol v ss l2_ rxdata6 v ddd2 v ddd2 v ddd2 l2_ txcomp v ss l2_ rxdata4 l2_ rxdata5 l3_ rxdatak l3_ rxidle l2_ txdatak l2_ txidle l2_ txdata4 l2_ rxdata2 l2_ rxdata3 v ss l3_ rxdata6 l2_ txdata1 v ss l2_ txdata3 l2_ txdata6 v ss l2_ rxdata1 l3_ rxdata5 l3_ rxdata7 l2_ txdata0 l2_ txdata2 l2_ txdata5 l2_ txdata7 l2_ rxdata0 l0_ rxstatus0 l0_ rxstatus1 l1_ rxstatus1 l1_ rxstatus2 l2_ rxstatus0 l2_ rxstatus1 l2_ rxstatus2 l3_ rxstatus0 l3_ rxstatus1 deskew_ valid v ss vrefs px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 7 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 7.2 pin description the phy input and output pins are described in t ab le 4 to t ab le 11 . note that input and output is de?ned from the perspective of the phy. thus a signal on a pin described as an output is driven by the phy and a signal on a pin described as an input is received by the phy. a basic description of each pin is provided. signals named lx_*, designate the per-lane signal where x = (0 to 3). for example, lx_rx_p expands to the following signals l0_rx_p, l1_rx_p, l2_rx_p and l3_rx_p. all sstl signaling is 2.5 v or 1.8 v selectable. [1] as pcie speci?cation de?ned. table 4. pci express serial data lines symbol pin type signaling description l0_rx_p d1 input pcie i/o lane 0 differential input receive pair with 50 w on-chip termination [1] l0_rx_n e1 input pcie i/o l0_tx_p f3 output pcie i/o lane 0 differential output transmit pair with 50 w on-chip termination [1] l0_tx_n g3 output pcie i/o l1_rx_p g1 input pcie i/o lane 1 differential input receive pair with 50 w on-chip termination l1_rx_n h1 input pcie i/o l1_tx_p j3 output pcie i/o lane 1 differential output transmit pair with 50 w on-chip termination l1_tx_n k3 output pcie i/o l2_rx_p k1 input pcie i/o lane 2 differential input receive pair with 50 w on-chip termination l2_rx_n l1 input pcie i/o l2_tx_p m3 output pcie i/o lane 2 differential output transmit pair with 50 w on-chip termination l2_tx_n n3 output pcie i/o l3_rx_p n1 input pcie i/o lane 3 differential input receive pair with 50 w on-chip termination l3_rx_n p1 input pcie i/o l3_tx_p t1 output pcie i/o lane 3 differential output transmit pair with 50 w on-chip termination l3_tx_n u1 output pcie i/o table 5. pxpipe interface transmit data signals symbol pin type signaling description l0_txdata[7:0] a9, b9, a10, a11, b11, a12, b12, c12 input sstl 8-bit transmit data input from the mac to the phy lane 0 l0_txdatak c10 input sstl selection input for the symbols of transmit data at lane 0; low = data byte; high = control byte l1_txdata[7:0] g17, h17, h16, j17, j16, k17, l16, l17 input sstl 8-bit transmit data input from the mac to the phy lane 1 l1_txdatak k15 input sstl selection input for the symbols of transmit data at lane 1; low = data byte; high = control byte px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 8 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy l2_txdata[7:0] u16, t15, u15, r14, t14, u13, t12, u12 input sstl 8-bit transmit data input from the mac to the phy lane 2 l2_txdatak r12 input sstl selection input for the symbols of transmit data at lane 2; low = data byte; high = control byte l3_txdata[7:0] u6, t6, u5, t5, u4, u3, t3, r3 input sstl 8-bit transmit data input from the mac to the phy lane 3 l3_txdatak r5 input sstl selection input for the symbols of transmit data at lane 3; low = data byte; high = control byte table 6. pxpipe interface receive data signals symbol pin type signaling description l0_rxdata[7:0] a4, b5, a5, a6, b6, a7, b8, a8 output sstl 8-bit receive data output from the phy lane 0 to the mac l0_rxdatak c4 output sstl selection output for the symbols of receive data at lane 0; low = data byte; high = control byte l1_rxdata[7:0] a16, a17, b17, c17, d17, e17, f16, f17 output sstl 8-bit receive data output from the phy lane 1 to the mac l1_rxdatak c16 output sstl selection output for the symbols of receive data at lane 1; low = data byte; high = control byte l2_rxdata[7:0] m17, n17, p17, p16, r17, r16, t17, u17 output sstl 8-bit receive data output from the phy lane 2 to the mac l2_rxdatak m16 output sstl selection output for the symbols of receive data at lane 2; low = data byte; high = control byte l3_rxdata[7:0] u11, t11, u10, u9, t9, t8, u8, u7 output sstl 8-bit receive data output from the phy lane 3 to the mac l3_rxdatak r10 output sstl selection output for the symbols of receive data at lane 3; low = data byte; high = control byte table 5. pxpipe interface transmit data signals continued symbol pin type signaling description px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 9 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy table 7. pxpipe interface command signals symbol pin type signaling description l0_txidle c11 input sstl forces lane 0 tx output to electrical idle (see t ab le 13 ) l1_txidle l15 input sstl forces lane 1 tx output to electrical idle (see t ab le 13 ) l2_txidle r13 input sstl forces lane 2 tx output to electrical idle (see t ab le 13 ) l3_txidle r4 input sstl forces lane 3 tx output to electrical idle (see t ab le 13 ) l0_txcomp c9 input sstl used when transmitting the compliance pattern at lane 0; high-level sets the running disparity to negative l1_txcomp l14 input sstl used when transmitting the compliance pattern at lane 1; high-level sets the running disparity to negative l2_txcomp p13 input sstl used when transmitting the compliance pattern at lane 2; high-level sets the running disparity to negative l3_txcomp p4 input sstl used when transmitting the compliance pattern at lane 3; high-level sets the running disparity to negative l0_rxpol c8 input sstl signals the phy to perform a polarity inversion on the receive data at lane 0; low = phy does no polarity inversion; high = phy does polarity inversion l1_rxpol j15 input sstl signals the phy to perform a polarity inversion on the receive data at lane 1; low = phy does no polarity inversion; high = phy does polarity inversion l2_rxpol n14 input sstl signals the phy to perform a polarity inversion on the receive data at lane 2; low = phy does no polarity inversion; high = phy does polarity inversion l3_rxpol p5 input sstl signals the phy to perform a polarity inversion on the receive data at lane 3; low = phy does no polarity inversion; high = phy does polarity inversion reset_n a13 input sstl phy reset input; active low rxdet_ loopb e15 input sstl instructs the phy to begin a receiver detection operation or to begin loopback; low = reset state pwrdwn0 c14 input sstl transceiver power-up and power-down inputs (see t ab le 12 ); 0x2 = reset state pwrdwn1 b14 input sstl deskew_ start b15 input sstl signals the phy to start a lane to lane deskew (see t ab le 15 ); low = reset state lanerevers e14 input sstl signals the phy to perform lane reversal (see t ab le 15 ), low = reset state px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 10 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy pipeloopb c13 input sstl signals the phy to do loopback at pxpipe side (see t ab le 15 ), low = reset state pipesel d13 input sstl signals the phy to switch from pxpipe to pipe interface, low = reset state encoden d12 input sstl enable the internal encoder to replace side-band signals to perform selected functions (see t ab le 15 ) table 8. pxpipe interface status signals symbol pin type signaling description l0_rxvalid c7 output sstl indicates symbol lock and valid data on rx_data and rx_datak at lane 0 l1_rxvalid f14 output sstl indicates symbol lock and valid data on rx_data and rx_datak at lane 1 l2_rxvalid m14 output sstl indicates symbol lock and valid data on rx_data and rx_datak at lane 2 l3_rxvalid r6 output sstl indicates symbol lock and valid data on rx_data and rx_datak at lane 3 l0_rxidle d4 output sstl indicates receiver detection of an electrical idle at lane 0; this is an asynchronous signal l1_rxidle d16 output sstl indicates receiver detection of an electrical idle at lane 1; this is an asynchronous signal l2_rxidle m15 output sstl indicates receiver detection of an electrical idle at lane 2; this is an asynchronous signal l3_rxidle r11 output sstl indicates receiver detection of an electrical idle at lane 3; this is an asynchronous signal l0_rxstatus0 c6 output sstl encodes receiver status and error codes for the received data stream and receiver detection at lane 0 (see t ab le 14 ) l0_rxstatus1 c5 output sstl l0_rxstatus2 d5 output sstl l1_rxstatus0 h15 output sstl encodes receiver status and error codes for the received data stream and receiver detection at lane 1 (see t ab le 14 ) l1_rxstatus1 g15 output sstl l1_rxstatus2 f15 output sstl l2_rxstatus0 r15 output sstl encodes receiver status and error codes for the received data stream and receiver detection at lane 2 (see t ab le 14 ) l2_rxstatus1 p15 output sstl l2_rxstatus2 n15 output sstl l3_rxstatus0 r7 output sstl encodes receiver status and error codes for the received data stream and receiver detection at lane 3 (see t ab le 14 ) l3_rxstatus1 r8 output sstl l3_rxstatus2 r9 output sstl deskew_valid c15 output sstl indicates the lane deskew is completed and passed (see t ab le 15 ) phystatus d15 output sstl used to communicate completion of several phy functions including power management state transitions and receiver detection table 7. pxpipe interface command signals continued symbol pin type signaling description px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 11 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy table 9. clock and reference signals symbol pin type signaling description txclk a15 input sstl source synchronous 250 mhz transmit clock input from mac. all input data and signals to the phy are synchronized to this clock. rxclk a14 output sstl source synchronous 250 mhz clock output for received data and status signals bound for the mac. refclk_p a1 input pcie i/o 100 mhz reference clock input. this is the spread spectrum source clock for pci express. differential pair input with 50 w on-chip termination. refclk_n b1 input pcie i/o pvt d3 - analog i/o input or output to create a compensation signal internally that will adjust the i/o pads characteristics as pvt drifts. connect to v dd through a 49.9 w resistor. vrefs u14 input reference voltage input for sstl signaling. connect to 900 mv for sstl_18, to 1.25 v for sstl_2. table 10. 3.3 v jtag signals symbol pin type signaling description tms a2 input 3.3 v cmos test mode select input trst_n b2 input 3.3 v cmos test reset input for the jtag interface; active low. pull-down required for normal operation tck b3 input 3.3 v cmos test clock input for the jtag interface tdi a3 input 3.3 v cmos test data input tdo c3 output 3.3 v cmos test data output table 11. pci express phy power supplies symbol pin type signaling description v dda1 j4, k4, l4, m4, n4 power 1.2 v analog power supply for serializer and de-serializer v dda2 e4 power 3.3 v analog power supply for serializer and de-serializer v ddd1 c2 power 3.3 v power supply for jtag i/o v ddd2 d7, d8, d10, d11, g14, h14, j14, k14, p10, p11, p12 power 2.5 v or 1.8 v power supply for sstl i/o px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 12 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 8. functional description the main function of the phy is to convert digital data into electrical signals and vice versa. the pci express phy handles the low level pci express protocol and signaling. the px1041a pci express phy consists of the physical coding sub-layer (pcs), a serializer and de-serializer (serdes) and a set of i/os (pads). the pci express phy handles the low level pci express protocol and signaling. this includes features such as clock and data recovery (cdr), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection. the pxpipe interface between the mac and px1041a is a superset of the phy interface for the pci express (pipe) speci?cation. the following feature have been added: ? source synchronous clocks for rx and tx data to simplify timing closure. the 4 8-bit data width pxpipe interface operates at 250 mhz with sstl class i signaling at 2.5 v or 1.8 v. px1041a does not integrate sstl termination resistors inside the ic. each pci express lane consists of a differential input pair and a differential output pair. the data rate per lane is 2.5 gbit/s. 8.1 receiving data incoming data enters the chip at the rx interface. the receiver converts these signals from small-amplitude differential signals into rail-to-rail digital signals. the carrier detect circuit detects whether data is present on the line and passes this information through to the serdes and pcs. if a valid stream of data is present the clock and data recovery unit (cdr) ?rst recovers the clock from the data and then uses this clock for re-timing the data (i.e., recovering the data). the de-serializer or serial-to-parallel converter (s2p) de-serializes this data into 10-bits parallel data. since the s2p has no knowledge about the data, the word alignment is still random. this is ?xed in the digital domain by the pcs block. it ?rst detects a 10-bit comma character (k28.5) from the random data stream and aligns the bits. then it converts the 10-bit raw v ddd3 p7, p8 power 1.2 v power supply for core v dd f4, g4, h4 power 1.2 v power supply for high-speed serial pci express i/o pads and pvt v ss b4, b7, b10, b13, b16, c1, d2, d6, d9, d14, e2, e3, e16, f1, f2, g2, g16, h2, h3, j1, j2, k2, k16, l2, l3, m1, m2, n2, n16, p2, p3, p6, p9, p14, r1, r2, t2, t4, t7, t10, t13, t16, u2 ground ground table 11. pci express phy power supplies continued symbol pin type signaling description px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 13 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy data into 8-bit words using 8b/10b decoding. an elastic buffer and fifo brings the resulting data to the right clock domain, which is the rx source synchronous clock domain. 8.2 transmitting data when the phy transmits, it receives 4 8-bit data from the mac. this data is encoded using an 8b/10b encoding algorithm. the 2 bits overhead of the 8b/10b encoding ensures the serial data will be dc-balanced and has a suf?cient 0-to-1 and 1-to-0 transition density for clock recovery at the receiver side. the serializer or parallel-to-serial converter (p2s) serializes the 10 bits data into serial data streams. these data streams are latched into the transmitter, where they are converted into small amplitude differential signals. the transmitter has built-in de-emphasis for a larger eye opening at the receiver side. the pll has a suf?ciently high bandwidth to handle a 100 mhz reference clock with a 30 khz to 33 khz spread spectrum modulation. 8.3 clocking there are three clock signals used by the px1041a: ? refclk is a 100 mhz external reference clock that the phy uses to generate the 250 mhz data clock and the internal bit rate clock. this clock may have 30 khz to 33 khz spread spectrum clock (ssc) modulation. ? txclk is a reference clock that the phy uses to clock the txdata and command. this source synchronous clock is provided by the mac. the phy expects that the rising edge of txclk is centered to the data. the txclk has to be the same frequency as rxclk. ? rxclk is a source synchronous clock provided by the phy. the rxdata and status signals are synchronous to this clock. the phy aligns the rising edge of rxclk to the center of the data. rxclk may be used by the mac to clock its internal logic. 8.4 reset the phy must be held in reset until power and refclk are stable. it takes the phy 64 m s maximum to stabilize its internal clocks. rxclk frequency is the same as refclk frequency, 100 mhz, during this time. the phy de-asserts phystatus when internal clocks are stable. the pipe speci?cation recommends that while reset_n is asserted, the mac should have rxdet_loopb de-asserted, txidle asserted, txcomp de-asserted, rxpol de-asserted and power state p1. the mac can also assert a reset if it receives a physical layer reset packet. px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 14 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 8.5 power management the power management signals allow the phy to manage power consumption. the phy meets all timing constraints provided in the pci express base speci?cation regarding clock recovery and link training for the various power states. four power states are de?ned: p0, p0s, p1 and p2. p0 state is the normal operational state for the phy. when directed from p0 to a lower power state, the phy can immediately take whatever power saving measures are appropriate. in states p0, p0s and p1, the phy keeps internal clocks operational. for all state transitions between these three states, the phy indicates successful transition into the designated power state by a single cycle assertion of phystatus. for all power state transitions, the mac must not begin any operational sequences or further power state transitions until the phy has indicated that the initial state transition is completed. txidle should be asserted while in power states p0s and p1. ? p0 state: all internal clocks in the phy are operational. p0 is the only state where the phy transmits and receives pci express signaling. p0 is the appropriate phy power management state for most states in the link training and status state machine (ltssm). exceptions are listed for each lower power phy state (p0s, p1 and p2). ? p0s state : the mac will move the phy to this state only when the transmit channel is idle. while the phy is in either p0 or p0s power states, if the receiver is detecting an electrical idle, the receiver portion of the phy can take appropriate power saving measures. note that the phy is capable of obtaining bit and symbol lock within the phy-speci?ed time (n_fts with or without common clock) upon resumption of signaling on the receive channel. this requirement only applies if the receiver had previously been bit and symbol locked while in p0 or p0s states. ? p1 state : selected internal clocks in the phy are turned off. the mac will move the phy to this state only when both transmit and receive channels are idle. the phy indicates a successful entry into p1 (by asserting phystatus). p1 should be used for the disabled state, all detect states, and l1.idle state of the link training and status state machine (ltssm). ? p2 state : phy will enter p2 and power down the tx and the rx plls. rxclk is turned off and the phy interface is in asynchronous mode. the phy still uses main power and cannot receive or transmit beacon. fig 4. reset 002aac172 rxclk reset_n phystatus 100 mhz 250 mhz px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 15 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy [1] txidle = 0 [2] txidle = 1 8.6 receiver detect when the phy is in the p1 state, it can be instructed to perform a receiver detection operation to determine if there is a receiver at the other end of the link. basic operation of receiver detection is that the mac requests the phy to do a receiver detect sequence by asserting rxdet_loopb. when the phy has completed the receiver detect sequence, each lane drives its own rxstatus signals to the value of 011b if a receiver is present, or to 000b if there is no receiver. then the phy will assert phystatus to indicate the completion of receiver detect operation. the mac uses the rising edge of phystatus to sample each lanes rxstatus signals and then de-asserts rxdet_loopb. a few cycles after the rxdet_loopb de-asserts, the phystatus is also de-asserted. table 12. summary of power management state pwrdwn[1:0] power management state transmitter receiver tx pll rxclk rx pll/cdr 00b p0, normal operation on [1] on on on on 01b p0s, power saving state idle [2] idle on on on 10b p1, lower power state idle [2] idle on on off 11b p2, lowest power state idle [2] idle off off off fig 5. receiver detect - receiver present 002aac173 rxclk 000b 10b 011b 000b phystatus rxstatus2, rxstatus1, rxstatus0 txclk rxdet_loopb pwrdwn1, pwrdwn0 px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 16 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 8.7 loopback the phy supports an internal loopback from the pci express receiver to the transmitter of every lane with the following characteristics. the phy retransmits each 10-bit data and control symbol exactly as received, without applying scrambling or descrambling or disparity corrections, with the following rules: ? if a received 10-bit symbol is determined to be an invalid 10-bit code (i.e., no legal translation to a control or data value possible), the phy still retransmits the symbol exactly as it was received. ? if a skp ordered set retransmission requires adding a skp symbol to accommodate timing tolerance correction, any disparity can be chosen for the skp symbol. ? the phy continues to provide the received data on the pxpipe interface, behaving exactly like normal data reception. ? the phy transitions from normal transmission of data from the pxpipe interface to looping back the received data at a symbol boundary. the phy begins to loopback data when the mac asserts rxdet_loopb while doing normal data transmission. the phy stops transmitting data from the pxpipe interface, and begins to loopback received symbols. while doing loopback, the phy continues to present received data on the pxpipe interface. the phy stops looping back received data when the mac de-asserts rxdet_loopb. transmission of data on the parallel interface begins immediately. since rxdet_loopb is a share signal, all lanes enter and exit the loopback mode at the same time. the timing diagram of figure 6 shows example timing for beginning loopback. in this example, the receiver is receiving a repeating stream of bytes, rx-a through rx-z. similarly, the mac is causing the phy to transmit a repeating stream of bytes tx-a through tx-z. when the mac asserts rxdet_loopb to the phy, the phy begins to loopback the received data to the differential tx_p and tx_n lines. fig 6. loopback start rxdet_loopb 002aac174 rxclk txclk rx-c rx-d rx-e rx-f rx-g tx-m tx-n tx-o tx-p tx-q tx-m tx-n rx-e tx_p, tx_n rxdata[7:0] txdata[7:0] px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 17 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy the timing diagram of figure 7 shows an example of switching from loopback mode to normal mode. as soon as the mac detects an electrical idle ordered-set, the mac de-asserts rxdet_loopb, asserts txidle and changes the powerdown signals to state p1. 8.8 electrical idle and lane turn off the pci express base speci?cation requires that devices send an electrical idle ordered-set before tx goes to the electrical idle state. the timing diagram of figure 8 shows an example of timing for entering electrical idle. fig 7. loopback end rxdet_loopb 001aac785 rxclk rxdata[7:0] txidle tx_p, tx_n txclk com idl junk looped back rx data junk includes electrical idle ordered set fig 8. electrical idle txidle 002aac175 txclk txdata[7:0] txdatak sczero com idl active (ends with electrical idle ordered-set) tx_p, tx_n px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 18 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy t ab le 13 summarizes the function of some pxpipe control signals. the mac can disable one or more lanes which are not in use. the mac asserts both lx_txidle and lx_txcomp at the same time to instruct the phy to turn off the corresponding lane x. the disabled lane(s) of the phy will ignore all other signals from the mac, except reset_n. the mac will ignore any signals from the disabled lane(s). when the mac wants to turn on the disabled lane(s), it must reset the whole phy as described in section 8.4 . 8.9 clock tolerance compensation the phy receiver contains an elastic buffer used to compensate for differences in frequencies between bit rates at the two ends of a link. the elastic buffer is capable of holding at least seven symbols to handle worst case differences (600 ppm) in frequency and worst case intervals between skp ordered-sets. the phy is responsible for inserting or removing skp symbols in the received data stream to avoid elastic buffer over?ow or under?ow. the phy monitors the receive data stream, and when a skip ordered-set is received, the phy can add or remove one skp symbol from each skp ordered-set as appropriate to manage its elastic buffer. whenever a skp symbol is added or removed, the phy will signal this to the mac using the rxstatus signals. these signals have a non-zero value for one clock cycle and indicate whether a skp symbol was added or removed from the received skp ordered-set. rxstatus should be asserted during the clock cycle when the com symbol of the skp ordered-set is moved across the parallel interface. if the removal of a skp symbol causes no skp symbols to be transferred across the parallel interface, then rxstatus is asserted at the same time that the com symbol (that was part of the received skip ordered-set) is transmitted across the parallel interface. figure 9 shows a sequence where the phy inserted a skp symbol in the data stream. figure 10 shows a sequence where the phy removed a skp symbol from a skp ordered-set. table 13. control signals function summary pwrdwn[1:0] rxdet_loopb txidle function description p0: 00b 0 0 normal operation 0 1 transmitter in idle 1 0 loopback mode 1 1 illegal p0s: 01b x 0 illegal 1 transmitter in idle p1: 10b x 0 illegal 0 1 transmitter in idle 1 1 receiver detect p2: 11b x x transmitter and receiver turned off. remark: beacon transmission and reception are not supported. px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 19 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 8.10 error detection the phy is capable of detecting receive errors of several types. these errors are signaled per lane to the mac layer using the receiver status signals lx_rxstatus. because of higher level error detection mechanisms (like crc) built into the data link layer of pci express, there is no need to speci?cally identify symbols with errors. however, timing information about when the error occurred in the data stream is important. when a receive error occurs, the appropriate error code is asserted for one clock cycle at the point closest to where the error actually occurred. fig 9. clock correction - insert a skp fig 10. clock correction - remove a skp 001aac779 rxclk active com skp 000b 001b 000b skp active rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 002aac176 rxclk active com skp 000b 010b 000b active rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 table 14. function table pxpipe status interface signals operating mode output pin rxstatus2 rxstatus1 rxstatus0 received data ok l l l one skp added l l h one skp removed l h l receiver detected l h h 8b/10b decode error h l l elastic buffer over?ow h l h elastic buffer under?ow h h l receive disparity error h h h px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 20 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy there are four error conditions that can be encoded on the rxstatus signals. if more than one error should happen to occur on a received byte, the errors are signaled with the priority shown below. 1. 8b/10b decode error 2. elastic buffer over?ow 3. elastic buffer under?ow 4. disparity error 8.10.1 8b/10b decode errors for a detected 8b/10b decode error, the phy places an edb (end bad) symbol in the data stream in place of the bad byte, and encodes rxstatus with a decode error during the clock cycle when the effected byte is transferred across the parallel interface. in figure 11 the receiver is receiving a stream of bytes rx-a through rx-z, and byte rx-c has an 8b/10b decode error. in place of that byte, the phy places an edb on the parallel interface, and sets rxstatus to the 8b/10b decode error code. note that a byte that cannot be decoded may also have bad disparity, but the 8b/10b error has precedence. 8.10.2 disparity errors for a detected disparity error, the phy asserts rxstatus with the disparity error code during the clock cycle when the effected byte is transferred across the parallel interface. in figure 12 the receiver detected a disparity error on rx-c data byte, and indicates this with the assertion of rxstatus. fig 11. 8b/10b decode errors 001aac780 rxclk rx-a rx-b edb 000b 100b 000b rx-d rx-e rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 fig 12. disparity errors 001aac781 rxclk rx-a rx-b rx-c 000b 111b 000b rx-d rx-e rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 21 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 8.10.3 elastic buffer for elastic buffer errors, an under?ow is signaled during the clock cycle when the spurious symbol is moved across the parallel interface. the symbol moved across the interface is the edb symbol. in the timing diagram figure 13 , the phy is receiving a repeating set of symbols rx-a through rx-z. the elastic buffer under?ow causing the edb symbol to be inserted between the rx-c and rx-d symbols. the phy drives rxstatus to indicate buffer under?ow during the clock cycle when the edb is presented on the parallel interface. for an elastic buffer over?ow, the over?ow is signaled during the clock cycle where the dropped symbol would have appeared in the data stream. in the timing diagram of figure 14 , the phy is receiving a repeating set of symbols rx-a through rx-z. the elastic buffer over?ows causing the symbol rx-d to be discarded. the phy drives rxstatus to indicate buffer over?ow during the clock cycle when rx-d would have appeared on the parallel interface. fig 13. elastic buffer under?ow fig 14. elastic buffer over?ow 001aac782 rxclk rx-a rx-b rx-c 000b 110b 000b edb rx-d rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 001aac783 rxclk rx-a rx-b rx-c 000b 101b 000b rx-e rx-f rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 22 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 8.11 polarity inversion the phy supports lane polarity inversion for each lane. the phy inverts received data for the lane which has its corresponding lx_rxpol asserted. the phy begins data inversion within 20 symbols after rxpol is asserted. 8.12 setting negative disparity to set the running disparity to negative, the mac asserts the corresponding lx_txcomp for one clock cycle that matches with the data that is to be transmitted with negative disparity. 8.13 jtag boundary scan interface joint test action group (jtag) or ieee 1149.1 is a standard, specifying how to control and monitor the pins of compliant devices on a printed-circuit board. this standard is commonly known as jtag boundary scan. this standard de?nes a 5-pin serial protocol for accessing and controlling the signal levels on the pins of a digital circuit, and has some extensions for testing the internal circuitry on the chip itself, which is beyond the scope of this data sheet. access to the jtag interface is provided to the customer for the sole purpose of using boundary scan for interconnect test veri?cation between other compliant devices that may reside on the board. using jtag for purposes other than boundary scan may produce undesired effects. fig 15. polarity inversion 001aac786 rxclk d21.5 d21.5 d10.2 d10.2 rxpol rxvalid rxdata[7:0] fig 16. setting negative disparity 002aac177 txclk data k28.5 k28.5 valid data k28.5 - k28.5 + k28.5 k28.5 tx_p, tx_n txcomp txdata[7:0] byte transmitted with negative disparity px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 23 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy the jtag interface is a 3.3 v cmos signaling. jtag trst_n must be asserted low for normal device operation. if jtag is not planned to be used, it is recommended to pull down trst_n and other jtag input signals to v ss via resistors. 8.14 optional functions the phy supports some optional functions: ? lane-to-lane deskew ? lane reversal ? pxpipe-side parallel loopback ? pipe mode select these features can be activated by either the side-band signals or the in-band encoded commands. when encoden pin is set to low, all functions will be controlled by the dedicated side-band signal pins; when encoden pin is set to high, the phy expects encoded commands to activate the required function. any activity on the corresponding pins will be ignored. t ab le 15 summarizes these optional functions. the principle of the in-band signaling is based on the use of some invalid 8b/10b special character symbols as encoded commands. t ab le 16 summarizes the encoded commands, and t ab le 17 is for the status signals. table 15. optional functions summary side-band signals encoden = 0 encoden = 1 deskew_start 1 = start lane-to-lane deskew dont care; phy expects an encoded command deskew_valid 1 = indicates deskew operation is completed and passed dont care; phy expects an encoded command lanerevers 1 = causes all lanes to reverse dont care; phy expects an encoded command pipesel 0 = pxpipe interface selected 1 = pipe interface selected 0 = pxpipe interface selected 1 = pipe interface selected pipeloopb 1 = at pxpipe side, txdata[7:0] directly loopback to rxdata[7:0] 0 = phy expects an encoded command 1 = reserved px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 24 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy the phy has priority to choose the physical lane 0 as the master lane, unless the lane has been turned off. the encoded commands and status signals should go to l0_txdata and l0_rxdata, and affect all four lanes. if lane 0 is turned off, then the next highest physical lane becomes the master lane. 8.14.1 lane-to-lane deskew lane-to-lane deskewing is required by pcie speci?cation, and is typically implemented in the mac. when the phy offers the feature of receiver lane-to-lane deskew, the mac needs to instruct the phy to start the lane deskew function when it is needed. the phy will respond with some status signals. with the side-band signal, the phy will detect the rising edge of the deskew_start to start the deskew operation. the phy responds back by asserting deskew_valid for a single cycle if deskew is completed and passed. the mac needs a built-in counter to table 16. encoded commands command function encoded txdata[7:0], txdatak txdata7 txdata6 txdata5 txdata4 txdata3 txdata2 txdata1 txdata0 txdatak plain comma 101111001 comma with lane-to-lane deskew 1011110 1 1 comma with lane reversal 101111 1 01 comma with lane reversal and lane-to-lane deskew 101111 11 1 start pxpipe-side loopback 001000101 stop pxpipe-side loopback 000000101 table 17. encoded status command function encoded rxdata[7:0], rxdatak rxdata7 rxdata6 rxdata5 rxdata4 rxdata3 rxdata2 rxdata1 rxdata0 rxdatak lane-to-lane deskew completed and passed 100111111 lane-to-lane deskew completed but failed 100111101 performing lane-to-lane deskew 100111011 px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 25 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy check for the assertion of deskew_valid signal, and if the mac does not see this signal go valid within the 32 rxclk cycles time-out period, it considers the deskew failed and can reinstruct the phy to perform deskew by deasserting and reasserting deskew_start. using in-band signals, the mac send encoded lane-to-lane deskew command to phy, and the phy will respond with encoded status signal. if deskewing is successful, the mac then send the phy the special comma with bit 0 = 0, shown at t ab le 16 , to stop the deskew. if deskewing fails, the mac should ?rst stop the deskew, then may resend the encoded deskew start command to restart the deskew process. the phy internally arbitrates to decide the master lane to use for deskewing. all lanes that are turned off by the mac, do not take part in arbitration or deskewing. the phy has priority to choose lane 0 as the master lane, unless the lane has been turned off. even when lane reversal is enabled and physical lane 0 becomes logical lane 3, physical lane 0 still has priority for becoming the master. when the phy is con?gured to perform lane-to-lane deskew the information about skp insertion and removal from the phy should be ignored by the mac. this is because the deskewing is done by the phy and hence the skip insertion and removal information is not required. all other information like decode error, disparity error, fifo over?ow, fifo under?ow, and ok are valid. 8.14.2 lane reversal lane reversal for multi-lane implementation is particularly useful to ease pcb layout. it swaps the physical lane0, lane1, lane2, and lane3 to the logical lane3, lane2, lane1, and lane0, respectively. this feature is typically performed in the mac. px1041a has this optional built-in feature. it is required to have a signal from the mac to the phy to enable it. when the mac asserts lanerevers, the phy will enable the feature. alternatively, the mac can send the encoded command listed in t ab le 16 to enable this feature. 8.14.3 pxpipe-side parallel loopback the function of pxpipe-side parallel loopback is mainly for test debugging purposes to check the pcb connection between the mac and the phy. the phy will loopback any data that is present on the lx_txdata and lx_txdatak lines to the corresponding lx_rxdata and lx_rxdatak. pipeloopb being high will enable the feature, or the mac may use the encoded commands in t ab le 16 . this feature requires the phy to be in the p1 state. 8.14.4 pipe mode by default, the interface between the mac and px1041a is pxpipe, which has source synchronous clocks for transmit and receive data. the pipe mode, which uses a single clock, rxclk, for both transmit and receive, is selectable by setting the pipesel pin high. px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 26 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 9. limiting values [1] no select pin needed. [2] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic discharge association, rome, ny, usa. [3] charged device model: ansi/eos/esd-s5.3.1-1999, standard for esd sensitivity testing, charged device model - component level; electrostatic discharge association, rome, ny, usa. 10. thermal characteristics [1] signi?cant variations can be expected due to system variables, such as adjacent devices, or actual air ?ow across the package. table 18. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ddd1 digital supply voltage 1 for jtag i/o - 0.5 +4.6 v v ddd2 digital supply voltage 2 for sstl i/o [1] - 0.5 +3.75 v v ddd3 digital supply voltage 3 for core [1] - 0.5 +1.7 v v dd supply voltage for high-speed serial i/o and pvt - 0.5 +1.7 v v dda1 analog supply voltage 1 for serializer - 0.5 +1.7 v v dda2 analog supply voltage 2 for serializer - 0.5 +4.6 v v esd electrostatic discharge voltage hbm [2] - 2000 v cdm [3] - 500 v t stg storage temperature - 55 +150 c t j junction temperature - 55 +125 c t amb ambient temperature operating commercial 0 +70 c industrial - 40 +85 c table 19. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air, jedec test card [1] 32.6 k/w r th(j-c) thermal resistance from junction to case in free air, jedec test card [1] 6.9 k/w px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 27 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 11. characteristics table 20. pci express phy characteristics symbol parameter conditions min typ max unit supplies v ddd1 digital supply voltage 1 for jtag i/o 3.0 3.3 3.6 v v ddd2 digital supply voltage 2 for sstl_18 i/o 1.7 1.8 1.9 v v ddd2 digital supply voltage 2 for sstl_2 i/o 2.3 2.5 2.7 v v ddd3 digital supply voltage 3 for core 1.15 1.2 1.25 v v dd supply voltage for high-speed serial i/o and pvt 1.15 1.2 1.25 v v dda1 analog supply voltage 1 for serializer 1.15 1.2 1.25 v v dda2 analog supply voltage 2 for serializer 3.0 3.3 3.6 v i ddd1 digital supply current 1 for jtag i/o - px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 28 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy transmitter ui unit interval 399.88 400 400.12 ps v tx_diffp-p differential peak-to-peak output voltage 0.8 - 1.2 v t tx_eye_m-mjitter maximum time between the jitter median and maximum deviation from the median - px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 29 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy [1] reference voltage for sstl i/o. table 21. pxpipe characteristics symbol parameter conditions min typ max unit f rxclk rxclk frequency 249.925 250 250.075 mhz f txclk txclk frequency 249.925 250 250.075 mhz v vrefs voltage on pin vrefs for sstl_18 [1] - 900 - mv v vrefs voltage on pin vrefs for sstl_2 [1] - 1.25 - v v oh(sstl18) sstl_18 high-level output voltage v tt = 900 mv 1.50 - - v v ol(sstl18) sstl_18 low-level output voltage v tt = 900 mv - - 0.30 v v ih(sstl18) sstl_18 high-level ac input voltage v ref = 900 mv 1.15 - - v v il(sstl18) sstl_18 low-level ac input voltage v ref = 900 mv - - 0.65 v v oh(sstl2) sstl_2 high-level output voltage v tt = 1.25 v 1.85 - - v v ol(sstl2) sstl_2 low-level output voltage v tt = 1.25 v - - 0.64 v v ih(sstl2) sstl_2 high-level ac input voltage v ref = 1.25 v 1.56 - - v v il(sstl2) sstl_2 low-level ac input voltage v ref = 1.25 v - - 0.94 v input signals; measured with respect to txclk t su(tx)(pxpipe) setup time of pxpipe input signal see figure 17 500 - - ps t h(tx)(pxpipe) hold time of pxpipe input signal see figure 17 500 - - ps output signals; measured with respect to rxclk t su(rx)(pxpipe) setup time of pxpipe output signal see figure 17 1500 - - ps t h(rx)(pxpipe) hold time of pxpipe output signal see figure 17 1500 - - ps fig 17. de?nition of pxpipe timing pxpipe input txclk pxpipe output rxclk t h(rx)(pxpipe) t su(rx)(pxpipe) t h(tx)(pxpipe) t su(tx)(pxpipe) 002aac316 px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 30 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 12. package outline fig 18. package outline sot631-4 (lfbga208) references outline version european projection issue date iec jedec jeita sot631-4 mo-205 sot631-4 07-03-09 07-03-19 unit a max mm 1.5 0.4 0.3 1.10 0.95 15.1 14.9 15.1 14.9 0.8 12.8 0.15 0.08 0.1 a 1 dimensions (mm are the original dimensions) lfbga208: plastic low profile fine-pitch ball grid array package; 208 balls; body 15 x 15 x 1 mm 0 5 10 mm scale a 2 b 0.5 0.4 d e e e 1 e 2 12.8 v w y 0.12 y 1 c y c y 1 x e 2 e 1 e e b a c b ? v m c ? w m ball a1 index area 1 a b c d e f g h j k l m n p r t u 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 detail x a a 1 a 2 b a ball a1 index area e d px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 31 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 13. soldering this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus pbsn soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 32 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 13.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 19 ) than a pbsn process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 22 and 23 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 19 . table 22. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 23. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 33 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 14. abbreviations msl: moisture sensitivity level fig 19. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 24. abbreviations acronym description ber bit error rate bist built-in self test cmos complementary metal oxide semiconductor emi electromagnetic interference esd electrostatic discharge fpga field programmable gate array ltssm link training and status state machine mac media access control p2s parallel to serial pci peripheral component interconnect pcs physical coding sub-layer phy physical layer pll phase-locked loop pipe phy interface for the pci express pvt process voltage temperature rx receive s2p serial to parallel serdes serializer and de-serializer skp skip px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 34 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 15. references [1] pci express base speci?cation rev. 1.1 - pcisig [2] phy interface for the pci express architecture version 2.00 intel corporation 16. revision history ssc spread spectrum clock modulation sstl_18 stub series terminated logic for 1.8 volts sstl_2 stub series terminated logic for 2.5 volts tx transmit table 24. abbreviations continued acronym description table 25. revision history document id release date data sheet status change notice supersedes px1041a_1 20070621 objective data sheet - - px1041a_1 ? nxp b.v. 2007. all rights reserved. objective data sheet rev. 01 21 june 2007 35 of 36 nxp semiconductors px1041a pci express stand-alone x4 phy 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 17.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 17.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 18. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation. nxp semiconductors px1041a pci express stand-alone x4 phy ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 21 june 2007 document identifier: px1041a_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 pci express interface . . . . . . . . . . . . . . . . . . . . 1 2.2 phy/mac interface. . . . . . . . . . . . . . . . . . . . . . 1 2.3 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 power management . . . . . . . . . . . . . . . . . . . . . 2 2.5 clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.6 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 functional description . . . . . . . . . . . . . . . . . . 12 8.1 receiving data . . . . . . . . . . . . . . . . . . . . . . . . 12 8.2 transmitting data . . . . . . . . . . . . . . . . . . . . . . 13 8.3 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.5 power management . . . . . . . . . . . . . . . . . . . . 14 8.6 receiver detect. . . . . . . . . . . . . . . . . . . . . . . . 15 8.7 loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.8 electrical idle and lane turn off . . . . . . . . . . . . 17 8.9 clock tolerance compensation . . . . . . . . . . . . 18 8.10 error detection . . . . . . . . . . . . . . . . . . . . . . . . 19 8.10.1 8b/10b decode errors . . . . . . . . . . . . . . . . . . . 20 8.10.2 disparity errors . . . . . . . . . . . . . . . . . . . . . . . . 20 8.10.3 elastic buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.11 polarity inversion. . . . . . . . . . . . . . . . . . . . . . . 22 8.12 setting negative disparity . . . . . . . . . . . . . . . . 22 8.13 jtag boundary scan interface . . . . . . . . . . . . 22 8.14 optional functions . . . . . . . . . . . . . . . . . . . . . . 23 8.14.1 lane-to-lane deskew . . . . . . . . . . . . . . . . . . . 24 8.14.2 lane reversal . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.14.3 pxpipe-side parallel loopback . . . . . . . . . . . . 25 8.14.4 pipe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 10 thermal characteristics. . . . . . . . . . . . . . . . . . 26 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 27 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 31 13.2 wave and re?ow soldering . . . . . . . . . . . . . . . 31 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31 13.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 32 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33 15 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 34 17 legal information . . . . . . . . . . . . . . . . . . . . . . 35 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 35 17.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35 18 contact information . . . . . . . . . . . . . . . . . . . . 35 19 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 |
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